1. Field of Invention
The present invention is directed to a method of self-repairing manufacturing defects in semiconductor memories that are used as linked lists and apparatuses that perform this self-repair. Linked lists are often used in communication devices, such as a network switches and frame processors. While the present invention is discussed with respect to embodiments applicable to linked lists in communication devices, the present invention is applicable to any linked list based memory system.
More specifically, the present method diagnoses defective rows and columns of memories, and repairs a large number of the defects such that the operation of the memories is not affected by the defects. This method can significantly increase the manufacturing yield of communication devices by repairing their embedded memories that would be otherwise discarded as defective.
2. Description of Related Art
Most network switches or routers, or other packet or frame processing devices require large data storage memories that are embedded in semiconductor devices. These data storage memories are used to store and process packet data and values associated with the packet data. These memories are often operated as linked lists, which store packet data in a sequence of data elements that are linked by pointers. These memories must be tested for defects to ensure the proper operation of the device.
The probability of the memory failing due to a single defect or multiple defects dramatically increases as the memory size grows. The whole device is often discarded due to a single or small number of defects in the memory, leading the manufacturing yield of the device to an impractically low level. As memory sizes have increased along with increasing processing power, the problem of defects in memory is of greater concern.
Among prior solutions to the problem of improving memory yield, a row or column redundancy has been added to memories, so when a certain row or column failure is detected, the redundant row or column can replace the defective one. This technique, however, involves costly laser repair procedures and is also limited to repairing a small number of memory defects, often one or two defects.
An autonomous test method called a built-in self-test (BIST) has been used for memory testing. It consists of a pattern generator, a finite state machine that controls that pattern generator based on algorithms such as marching or checker board, and a comparator that checks whether the output data of the memory matches the expected patterns. While a BIST method can detect a defective row or column of a memory, a BIST method by itself does repair the detected row or column.
Therefore, there is a need for method and apparatus to repair defects in memory that is not limited in the number of row defects that it can correct for and also is capable of repairing column defects in memory. There is also a need for such an apparatus and method that repairs the defects without changing the physical circuit structure of the memory and is capable of detecting and repairing defects of the memory when its power is on.
The present invention provides an efficient solution to the problem of repairing both row defects and column defects in memories used as linked lists. The present invention repairs the memory by manipulating the defective row addresses and correcting column defects without changing the physical circuit structure, so it is a kind of logical repair. The present method diagnoses defective rows and columns of memories, and repairs a large number of the defects such that the operation of the memories is not affected by the defects.
According to one aspect of this invention, defective rows are identified and their addresses are stored in an extra storage called defect address registers. When a linked list is created for new packet data, the addresses stored in the internal registers are skipped and so are prevented from being used as new elements of linked list. This way, the defective rows are not encountered in the normal operation of the memory, so the memory with a certain number of defective rows is accepted as a good device, and thus the yield can be improved. This method logically repairs the defects of memories, whereas the laser repair technique physically repairs the defects. This logical repair technique is applicable to cases where a small number of defective rows needs to be repaired. A more enhanced solution is described below, which can repair column defects and also a large number of row defects.
According to one aspect of this invention, A process of repairing defects in linked list memories is disclosed. One of the linked list memories is selected as a defect marking memory and faults in rows of the defect marking memory are detected. Row addresses having at least one fault are stored in defect address registers when at least one fault in the rows of the defect marking memory is detected. Faults in rows of other linked list memories are detected, where the other linked list memories are the linked list memories other than the defect marking memory and a marking code is stored for each row address of the other linked list memories in the defect marking memory, where a particular marking code indicates whether a particular row address has at least one fault. The defect address registers and the defect marking memory are searched when addresses of the linked list memories are linked and row addresses indicated as having at least one fault are skipped in the linking process.
Alternatively, the process of repairing defects in the linked list memories may be performed when the linked list memories are powered-on and may be an automated process that does not require input from an external source. In addition, the process may also include the repair of defective columns of the linked list memories where one or more consecutive columns can be repaired. Also, the process may be applied to packet data linked list memories used in a network device, including a pointer memory and a packet data memory.
According to another embodiment of this invention, a process of repairing defective columns of a memory is also disclosed. The column defect repair process is performed by an error correction code aided repair system. The inputs of the memory are interleaved, and encoded using a partitioned error correction code generator. The outputs from the memory are received and the outputs are combined with an expected data pattern to produce logical outputs. The logical outputs are interleaved and a predetermined number of the interleaved logical outputs are compared. The outputs from the memory are flagged as faulty when the number of consecutive multiple bit errors is greater than a predetermined number. The defects that are not flagged are repaired by decoding the outputs of the memory using a partitioned error correction code generator and corrector. The defects that are flagged as faulty are beyond the capability of column repair and are repaired by the disclosed row repair process. The addresses are marked as faulty in a defect marking memory when the outputs from the memory are flagged as faulty. The defect marking memory is searched when addresses of the memory are accessed and column addresses indicated being faulty are skipped.
In another embodiment, a defect repair system for linked list memories is also disclosed. The system includes at least one built-in self-test unit, having an interface for accessing at least one linked list memories, a defect marking logic unit, in communication with the at least one built-in self-test unit and a defect marking memory, in communication with the defect marking logic unit. The system also includes a defect skipping logic unit, in communication with the defect marking and a linked list initializer, where the linked list initializer is in communication with the linked list memories and the linked list initializer uses data recorded in defect marking memory through the defect skipping logic unit to determine portions of the linked list memories to be skipped.
Alternatively, the defect repair system may be configured to repair defects when the linked list memories are powered-on. Also, the at least one built-in self-test unit may be an error correction code aided built-in self-test unit that is configured to repair defective columns of the linked list memories where one or more consecutive columns can be repaired. Also, the defect repair system may also have defect address registers and at least two built-in self-test units, with one of the at least two built-in self-test units being in communication with the defect marking memory and the defect address registers, and the one of the at least two built-in self-test units is configured to repair defects in the defect marking memory through use of the defect address registers.
In an additional embodiment, a network device having linked list memories is disclosed. The network device includes a port interface, for receiving and transmitting packet data, a plurality of packet data linked list memories, in communication with the port interface and a plurality of built-in self-test units, having interfaces for accessing the packet data linked list memories. The network device also includes a defect marking logic unit, in communication with the plurality of built-in self-test units, a defect marking memory, in communication with the defect marking logic unit, a defect skipping logic unit, in communication with the defect marking and a linked list initializer in communication with the packet data linked list memories. The linked list initializer uses data recorded in defect marking memory through the defect skipping logic unit to determine portions of the packet data linked list memories to be skipped.
These and other objects of the present invention will be described in or be apparent from the following description of the preferred embodiments.